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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12550-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89550A Series
MB89557A/558A/P558A/PV550A
s DESCRIPTION
The MB89550A series is a general-purpose, single-chip microcontroller that features a compact instruction set and contains a range of peripheral functions including a dual- clock control system, 5-level operating speed control, LCD controller driver, A/D converter, D/A converter, timer, serial interface, PWM timer, PWC timer, and external interrupts. The LCD controller driver is particularly suited for simultaneous control of LCD duty drive and static drive functions.
s FEATURES
* Range of package options * LQFP package (0.5 mm pitch) * TQFP package (0.4 mm pitch) * High speed operation at low voltage * Minimum instruction execution time 0.32 s (for 12.5 MHz oscillation) * F2MCR-8L CPU core Instruction set optimized for controller applications * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instructions * Bit manipulation instructions, etc.
s PACKAGE
100-pin Plastic LQFP 100-pin Plastic TQFP
(Continued)
100-pin Ceramic MQFP
(FPT-100P-M05)
(FPT-100P-M18)
(MQP-100C-P02)
MB89550A Series
(Continued)
* Dual-clock control system * Main clock 12.5 MHz maximum : (Four speed settings available, oscillation halts in sub-clock mode) * Sub-clock 32.768 kHz : (Operation clock for sub-clock mode) * 11 timer systems * 8/16-bit timer counter 1 (square wave output, 2-channel output switching available) * 8/16-bit timer counter 2 (square wave output, 2-channel output switching available) * 16-bit timer counter (also functions as event counter) * 8-bit PWM timer (8-bit PWM timer x 2 channels or PPG timer x 1 channel, includes event counter function) * 8-bit PWC timer (8-bit PWC timer x 1 channel) * 6-bit PPG timer (6-bit PPG timer x 1 channel) * 21-bit timebase timer * Clock prescaler (17-bit) * UART/serial interface * UART/SIO switching * UART * Clock synchronous/asynchronous switching available * 10-bit A/D converter * 10-bit A/D x 8 channels * 8-bit D/A converter * 8-bit D/A x 2 channels * External interrupts * Eight independent inputs can be used for recovery from low-power consumption modes (selection of rising, falling, or both edge detection functions). * Eight independent inputs can be used for recovery from low-power consumption modes (L level detection function included). * Clock output functions * High speed clock signal multiplied by 2 available as output from HCLK pin. * Low speed clock pulse output available from LCLK pin. * LCD controller driver * 32SEG x 4COM (maximum 128 pixels) 8 dedicated to segment output only 8 for port or segment use 16 for port, segment, or static use * Built-in step-up power supply for driving LCD (optionally available) * Low-power consumption modes (standby modes) * Stop mode (all oscillations halt in sub-clock mode, current consumption falls to almost zero) * Sleep mode (the CPU stops to reduce current consumption to approximately 1/3 of normal) * Clock mode (all operations other than the clock prescaler halt, current consumption is very low) * Sub clock mode (systems operate on sub-clock signals) * Maximum 66 I/O ports * General-purpose I/O ports (N-ch open drain) : 4 * General-purpose I/O ports (N-ch open drain) : 24 * [also function as LCD ports, with restrictions] * General purpose I/O ports (CMOS) : 38
2
MB89550A Series
s PRODUCT LINEUP
Part no. Parameter ROM size RAM size Packages Classification MB89P558A-201 MB89P558A-202 MB89P558A-203 48 KB 2 KB LQFP100 TQFP100 One-time product Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time MB89557A 32 KB 1 KB LQFP100 TQFP100 Mask ROM product MB89558A 48 KB 2 KB LQFP100 TQFP100 Mask ROM product MB89PV550A*-201 MB89PV550A*-202 MB89PV550A*-203 1 KB LQFP100 Evaluation product
CPU functions
: 136 : 8-bit : 1 to 3bytes : 1-, 8-, 16-bits : 0.32 s (at 12.5 MHz) : 2.88 s (at 12.5 MHz)
Ports 8/16-bit timer counter 1 8/16-bit timer counter 2 Peripheral Functions 16-bit timer counter PPWM timer PWC timer 6-bit PPG timer LCD controller driver UART UART/SIO A/D converter D/A converter Clock output Standby modes SIO
Output-only ports (N-ch open drain) General-purpose I/O ports (N-ch open drain) General-purpose I/O ports (CMOS) 2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer) with square wave output function 2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer) with square wave output function 16-bit timer/counter operation, 16-bit event counter operation 2-channel 8-bit PWM timer operation (also functions as 1-channel PPG timer) with event counter function 1-channel 8-bit PWC timer operation 1-channel 6-bit PWM timer operation Maximum 32SEGA~4COM (some ports provide selection of DUTY drive/STATIC drive/N-ch open drain I/O port functions) Switchable between UART (with clock synchronous/asynchronous data transfer function) and SIO (simple serial) Data transfer function for UART/SIO 8-channel 10-bit resolution 2-channel, 8-bit resolution High speed clock multipliedx2, and sub clock output available Sub clock mode, sleep mode, clock mode, and stop mode
* : The MB89PV550A provides only evaluation functions (functions for use with emulation tools). This model cannot use piggyback functions (functions for use with E2PROM).
3
MB89550A Series
s OPTIONS AND CORRESPONDING PRODUCTS
-201 Options LCD step-up circuit PORT/SEG dual-use pin selection Evaluation model No step-up circuit SEG8 to SEG31 : SEG/PORT dual use MB89PV550A-201 -202 Options -203 Options SEG8 to SEG21 : SEG/PORT dual use SEG22 to SEG31 : N-ch open drain*1 MB89PV550A-203 MB89P558A-203 MB89557A MB89558A Step-up circuit included SEG8 to SEG31 : SEG/PORT dual use MB89PV550A-202 MB89P558A-202 MB89557A MB89558A
MB89P558A-201 Model One-time model type MB89557A Mask ROM model*2 MB89558A
*1 : The SEG22-SEG31 pins (N-ch open drain) are not subject to the restriction that input voltage (VIN) must be less than the voltage at the V3 pin. *2 : Options may be specified at the time of mask ROM ordering.
s OSCILLATOR STABILIZATION WAIT TIME SELECTION
The MB89557A/558A allow a selection of default value for oscillator stabilization wait time, to be selected at the time of mask ROM ordering. Oscillator stabilization wait time selection Remarks 214/FCH 2 /FCH 218/FCH
17
1.31 ms (at F = 12.5 MHz) 10.48 ms (at F = 12.5 MHz) 20.97 ms (at F = 12.5 MHz)
4
MB89550A Series
s DIFFERENCES AMONG PRODUCTS AND PRECAUTIONS FOR MODEL SELECTION
* Package and Model Combinations Models MB89PV550A Package FPT-100P-M05 (LQFP-100 0.5 mm pitch) FPT-100P-M18 (TQFP-100 0.4 mm pitch) MQP-100C-P02 (MQFP-100 0.5 mm pitch) Note : Compatible with all options (-201/202/203) . * Memory Space * When evaluating chips using piggyback evaluators etc., please take note of the differences among products before making the evaluation. * Current Consumption * When operating at low speed, one-time PROM and EPROM products will consume more current than mask ROM products. However, the current consumption in sleep/stop modes is the same. * For specific details about each package, see "s PACKAGE DIMENSIONS". * For details about power consumption, see "s ELECTRICAL CHARACTERISTICS" . * Mask Options * The available options, and methods of using options, differ according to the model. Be sure to confirm the options from the "s MASK OPTIONS" section. * LCD Drive Step-up Power Circuit The MB89550A series is available with or without the step-up circuit option as a mask option. * Power Supply Path The models in the MB89550A series have two power supply pins, VCC1 and VCC2, with power supply paths that differ according to the model. Models Supply pin Power supply path MB89557A/ 558A MB89P558A VCC1 VCC2 VCC1 VCC2 VCC1 MB89PV550A VCC2 3V power supply pin for internal resource operation, including the CPU. 5V power supply pin for input/output ports. VPP pin for on-board writing. V power supply pin for internal resource operation, including the CPU, and for input/ output pins. Internally shut off, operates as input to VCC2 only. x x x x
MB89P558A
MB89557A MB89558A
5V power supply pin for internal resource operation, including the CPU, and for input/ output pins. * Oscillator Startup and Power-on Reset On the MB89PV550A and MB89P558A, oscillator startup and power-on reset are applied at the rise of the VCC2 input. On the MB89558A and MB89557A, oscillator startup and power-on reset are applied at the rise of the VCC1 input.
5
MB89550A Series
* Wide Register Functions The space available for use of wide register functions is as follows. MB89PV550A 2000H to FFFFH MB89P558A 4000H to FFFFH MB89558A 4000H to FFFFH MB89557A 8000H to FFFFH * The P40, P41, P84, P85 Pins On the MB889PV550A, an external oscillator signal equivalent to 64 clock pulses is required to initialize the P40, P41, P84, and P85 pins. Note therefore that at power-on there is an interval in which the values of these ports is undefined. On the MB89P558A, MB89558A, and MB89557A, these ports are set to "Hi-Z" status at power-on.
6
MB89550A Series
s PIN ASSIGNMENTS
(TOP VIEW)
SEG04 SEG03 VCC1 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC P46/SI P45/SO P44/SCK P43/PWM2 P42/PWM1/EC1 P41/TO12/HCLK P40/TO11/WTO P87/EC3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SEG05 SEG06 SEG07 P50/SEG08 VSS P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 P70/SEG24 P71/SEG25 P72/SEG26 P73/SEG27 P74/SEG28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P86/EC2/LCLK P85/TO22 P84/TO21 DVR DAOUT1 DAOUT2 P31 P30 P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/UCK P21/UO P20/UI P83/INT27 P82/INT26 P81/INT25 VSS P80/INT24 X1 X0 MODA X1A
P75/SEG29 P76/SEG30 P77/SEG31 AVR AVCC P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVSS P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 VCC2 P10/INT10 RST X0A
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(QFP-100)
7
MB89550A Series
s PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name SEG05 SEG06 SEG07 P50/ SEG08 VSS P51/ SEG09 P52/ SEG10 P53/ SEG11 P54/ SEG12 P55/ SEG13 P56/ SEG14 P57/ SEG15 P60/ SEG16 P61/ SEG17 P62/ SEG18 P63/ SEG19 P64/ SEG20 P65/ SEG21 P66/ SEG22 P67/ SEG23 P70/ SEG24 P71/ SEG25 N-ch open drain I/O pins. Also function as segment output pins for LCDC duty drive or static drive. G N-ch open drain I/O pins. Also function as segment output pins for LCDC duty drive. Circuit Type H H H G N-ch open drain I/O pin. Also functions as a segment output pin for LCDC duty drive. Power supply (GND) pin. Segment output pins for LCDC duty drive. Function
G
(Continued)
8
MB89550A Series
Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Pin Name P72/ SEG26 P73/ SEG27 P74/ SEG28 P75/ SEG29 P76/ SEG30 P77/ SEG31 AVR AVCC P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVSS P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 VCC2 P10/INT10 RST X0A X1A
Circuit Type
Function
G
N-ch open drain I/O pins. Also function as segment output pins for LCDC duty drive or static drive.

A/D converter reference voltage input pin. A/D converter and D/A converter power supply pin.
D
General purpose I/O ports. Also function as analog input pins.
A/D converter and D/A converter power supply pin (GND).
E
General purpose I/O ports. Also function as external interrupt 1 input pins. External interrupt 1 input signals are hysteresis signals (edge detection).
E I A
Power supply (5V) pin. General purpose I/O port. Also functions as an external interrupt 1 input pin. External interrupt 1 input signals are hysteresis signals (edge detection). Reset input pin. Crystal oscillator pins (32 KHz) .
(Continued)
9
MB89550A Series
Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
Pin Name MODA X0 X1 P80/INT24 VSS P81/INT25 P82/INT26 P83/INT27 P20/UI P21/UO P22/UCK P23/PPG1 P24/INT20 P25/INT21 P26/INT22 P27/INT23 P30 P31 DAOUT2 DAOUT1 DVR P84/TO21 P85/TO22 P86/EC2/ LCLK P87/EC3 P40/TO11/ WTO P41/TO12/ HCLK P42/ PWM1/ EC1 P43/PWM2
Circuit Type F A Operating mode setting pin.
Function
Crystal oscillator pins (Max12.5 MHz) . General purpose I/O port. Also functions as an external interrupt 2 input pin. External interrupt 2 input signals are hysteresis signals (level detection). Power supply (GND) pin. General purpose I/O ports. Also function as external interrupt 2 input pins. External interrupt 2 input signals are hysteresis signals (level detection). General purpose I/O ports. Also function as 8-bit serial I/O pins. General purpose I/O port. Also functions as the 6-bit PPG timer output. General purpose I/O ports. Also function as external interrupt 2 input pins. External interrupt 2 input signals are hysteresis signals (level detection).
E E E B E B
E
K C B E E
N-ch open drain I/O pins. D/A converter output pins. D/A converter reference voltage input pin. General purpose I/O ports. Also function as 8/16-bit timer pins. * P84 can be used as the output for the main clockx2 pulse. * P86 can be used as the event counter input or sub-clock pulse output. General purpose I/O port. Also functions as a 16-bit timer pin. General purpose I/O ports. Also function as 8/16-bit timer pins.
B
79 80 10
E B
General purpose I/O ports. Also function as PWM timer pins.
(Continued)
MB89550A Series
(Continued) Pin Circuit Pin Name No. Type
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P44/SCK P45/SO P46/SI P47/PWC C1 C0 V0 V1 V2 V3 COM0 COM1 COM2 COM3 SEG00 SEG01 SEG02 VCC1 SEG03 SEG04 H Power supply (3V) pin. Dedicated LCDC segment output pins. H Dedicated LCDC segment output pins. H Dedicated LCDC common output pins. LCD drive power supply pins. E B J J General purpose I/O port. Also functions as the PWC timer pin. Step-up voltage circuit capacitance connection pins. General purpose I/O ports. Also function as UART pins.
Function
11
MB89550A Series
s I/O CIRCUIT TYPES
Type
X1 (X1A)
Circuit
Remarks Oscillation feedback resistance * High speed side = approx. 1 M * Low speed side = approx. 4.5 M
A
X0 (X0A)
Main clock control signal (Sub-clock control signal) * CMOS I/O
R Pch Pch
Pull-up control register
B
Nch
Input control signal * D/A output Output enable C Analog output
R
Pch Pch
Pull-up control register
* A/D input * CMOS I/O
D
Nch
Input control signal
Port input Analog input
(Continued)
12
MB89550A Series
Type
R
Circuit Pull-up control register
Pch
Remarks * CMOS I/O * Hysteresis input (for external interrupt 0, 1, 2 input)
Pch
E
Nch
Input control signal
Port input Resource input * CMOS input Input * LCDC output * N-ch open drain I/O
F
Input control signal G
Port input
Nch
* LCDC output H
R Pch
* Hysteresis input * Pull-up resistance
I
Nch
Input * Hysteresis input * N-ch open drain I/O J
Nch
Resource input Input control signal Port input
(Continued)
13
MB89550A Series
(Continued) Type
Circuit
Remarks * N-ch open drain I/O
K
Nch
Input control signal
Port input
14
MB89550A Series
s HANDLING DEVICES
* Maximum rated voltage (Prevention of latchup) Be careful never to exceed maximum rated voltages. In CMOS IC devices, a condition known as latch-up may occur if voltages higher than Vcc or loser than Vss are applied to input or output pins other than medium- or high-voltage pins, or if the voltage applied between Vcc and Vss exceeds the rated voltage level. When latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVcc, AVR, and DVR) and analog input voltages do not exceed the digital power supply (Vcc). * Power supply voltages Power supply voltages should be kept as stable as possible. Rapid fluctuation of the voltage may cause the device to operate abnormally, even if the voltage remains within the allowed operating range. As a standard for power supply voltage stability, it is recommended that the peak-to-peak Vcc ripple voltage at commercial supply frequency (50 Hz to 60 Hz) be 10% or less of Vcc. Also when the power supply is turned on or off the transient voltage fluctuation be no more than 0.1V/ms or less. * Treatment of unused input pins Leaving unused input pins unconnected can cause abnormal operation. Unused input pins should always be pulled up or down. * Treatment of N.C. pins N.C. (not connected) pins should always be left open. * Treatment of power supply pins on devices with A/D or D/A converters Even when the A/D or D/A converters are not in use, be sure to make the necessary connections to ensure that AVCC = VCC, AVSS = AVR = DVR = VSS. * Precautions on using an external clock An oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop mode, even if an external clock is used. * Treatment of unused dedicated LCD pins Dedicated SEG output pins should be left open when not in use. * Handling of ports also used as segment pins When a ports is used as a segment pin, take care to ensure that the voltage applied to the pin does not exceed V3 (the segment drive voltage). This precaution is particularly necessary in models with step-up voltage circuits. Note also that after power-on or during a reset, an "L" level default signal is output form the segment/port pin. * Treatment of unused LCD pins Connect the V3 pin to VCC2. The other dedicated LCD pins V0, V1, V2, C0, and C1 should be pulled down. * Executing programs on RAM When programs are executed on RAM, debugging cannot be performed even with the use of the MB89PV550A. * Wild register functions Wild registers cannot be debugged with the MB89PV550A or tools. To verify operation, use the MB89P558A and perform in-place testing. 15
MB89550A Series
s PROGRAMMING SPECIFICATIONS FOR ONE-TIME PROM PRODUCTS
The MB89P558A has a "PROM mode" with functions equivalent to the MBM27C1001, that enables the microcontroller to be programmed by writing from a general-purpose ROM programmer with the use of a special adapter. Note however that electronic signature mode is not available. ROM Programmer Adapters With some ROM programmers the insertion of approximately 0.1F capacitance between VPP and VSS or between VCC and VSS allows more stable writing performance. The following table lists ROM programmer adapters. ROM Programmer Adapters Part No. MB89P558A * Inquiries Sun Hayato Co., Ltd.
Package FPT-100P-M05 FPT-100P-M18
Adapter Part No. ROM-100SQF-32DP-8LA2 ROM-100SQF-32DP-8LA
: TEL 03-3986-0403
* PROM Mode Memory Map The PROM mode memory map is shown below. PROM Mode Memory Map Normal operating mode
0000H I/O 0080H RAM 0880H
PROM mode (addresses on ROM programmer)
Not availablel
4000H 14000H
Program area (PROM)
Program area
(PROM)
FFFFH
1FFFFH
16
MB89550A Series
* EPROM Programming Procedure 1) Set the EPROM programmer type to MBM27C1001. 2) Load the program data into addresses 14000H to 1FFFFH in the EPROM programmer. 3) Use the EPROM programmer to program to addresses 14000H to 1FFFFH. * Recommended Screening Conditions High-temperature aging is the recommended method of screening unprogrammed one-time PROM microcontrollers before mounting. The flow of the screening process is shown below. Screening Flow
Program, verify
High-temperature aging +150 C, 48 h Read
Mount
* About Writing Yields The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.
17
MB89550A Series
s BLOCK DIAGRAM
X0 X1 X0A X1A
Main clock oscillator circuit & sub-clock oscillator circuit Clock control circuit Reset output circuit
21-bit time base timer 2-channel 8-bit PWM timer 8-bit timer counter 8-bit timer counter 8-bit timer counter 8-bit timer counter
P43/PWM2 P42/PWM1/EC1 P41/TO12/HCLK P40/TO11/WTO
CMOS I/O Port
RST V3 V0 C1, C0
Power-on reset & WDG circuit LCD display power generation and stepup circuit
P85/TO22 P84/TO21 P86/EC2/LCLK
Internal bus
Clock output
16-bit timer counter
P67/SEG23 P60/SEG16 P57/SEG15 P50/SEG08 SEG07 SEG00 COM3 COM0
LCD driver & N-ch OD I/O ports
P77/SEG31 P70/SEG24
LCD controller & driver control circuit
Static drive control circuit
P87/EC3 P23/PPG1 P20/UI P21/UO P22/UCK P44/SCK P45/SO
N-ch OD I/O ports
6 bit PPG UART/SIO
UART SIO CMOS I/O Port P83/INT27 P80/INT24 P27/INT23 P24/INT20 P17/INT17 P10/INT10
P46/SI P47/PWC DAOUT1 DAOUT2 DVR
External interrupt 2 (level) External interrupt 1 (edge)
RAM 1 K/2 Kbyte F2MC-8L CPU
Wild register circuit 6 byte
8-bit PWC timer
2-channel 8-bit D/A converter
CMOS I/O Port
8-channel 10-bit A/D converter
AVCC AVSS AVR
ROM 32 K/48 Kbyte
N-ch open drain I/O ports
P00/AN0 P07/AN7
Other pins
VSS VSS VCC1 VCC2 MODA
P30 P31
18
MB89550A Series
s CPU CORE
Memory space The MB89550A has 64 Kbytes of memory space, composed of the I/O area, RAM area, ROM area, and external area. The memory space includes general purpose registers, as well as areas used for special purposes such as vector tables. * I/O Area (address : 0000H to 007FH) * This area is allocated to control registers and data registers for internal peripheral functions. * Because the I/O area is part of memory space, it can be accessed in the same ways. Direct addressing provides faster access. * RAM Area * Static RAM is provided for use as an internal data area. * The size of internal RAM differs between product models. * High speed access is available to addresses 80H to FFH using direct addressing (the area available for use is restricted on some models). * Addresses 100H to 1FFH are used as the general-purpose register area. * If a reset is applied during writing to RAM, the value of date at the target addresses is not assured. * ROM Area * ROM is provided for use as the internal program area. * The size of internal ROM differs between product models. * Addresses FFC0H to FFFFH are used for special purpose data such as vector tables. Memory Map
MB89P558A MB89558A 0000H I/O 0080H RAM 0100H 0100H 0080H RAM 0100H I/O 0080H RAM 0000H I/O
MB89557A 0000H
MB89PV550A
Register
0200H 0480H 0200H 0480H
Register
0200H
Register
0480H
Wild register
0492H 0492H 0880H
Wild register
0492H RAM
Wild register
Not available
4000H 8000H ROM FFC0H FFFFH FFC0H FFFFH
Not available Not available
4000H
ROM FFC0H FFFFH
External ROM
Vector tables (Reset, interrupt, vector call instructions)
Vector tables (Reset, interrupt, vector call instructions)
Vector tables (Reset, interrupt, vector call instructions) 19
MB89550A Series
s I/O MAP
Address 00H 01H 02H 03H 04H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H T2CR#2 T1CR#1 T2DR#2 T1DR#1 T2CR#4 T1CR#3 T2DR#4 T1DR#3 SMC1 SRC1 PDR8 DDR8 Port 8 data register Port 8 direction register Unused area Timer 2 control register # 2(8/16-bit timer/counter -1) Timer 1 control register # 1(8/16-bit timer/counter -1) Timer 2 data register # 2(8/16-bit timer/counter -1) Timer 1 data register # 1(8/16-bit timer/counter -1) Timer 2 control register # 4(8/16-bit timer/counter -2) Timer 1 control register # 3(8/16-bit timer/counter -2) Timer 2 data register # 4(8/16-bit timer/counter -2) Timer 1 data register # 3(8/16-bit timer/counter -2) Serial mode control register 1 (UART) Serial rate control register (UART) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X 0 0 0 0 0 X 0B X 0 0 0 0 0 X 0B XXXXXXXXB XXXXXXXXB X 0 0 0 0 0 X 0B X 0 0 0 0 0 X 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B - - 0 1 1 0 0 0B PDR7 Port 7 data register Unused area R/W R/W XXXXXXXXB 0 0 0 0 0 0 0 0B PDR6 Port 6 data register Unused area R/W 0 0 0 0 0 0 0 0B SYCC STBC WDTC TBTC WPCR PDR2 DDR2 PDR3 PDR4 DDR4 PDR5 Standby control register Watchdog control register Time base time control register Clock prescaler control register Port 2 data register Port 2 direction register Port 3 data register Port 4 data register Port 4 direction register Port 5 data register Unused area R/W 0 0 0 0 0 0 0 0B Abbreviation PDR0 DDR0 PDR1 DDR1 Resister Name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register Unused area System clock control register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXX MM1 0 0B 0 0 0 1 0 XXXB 0XXXXXXXB X 0 XXX 0 0 0B X 0 XX 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B - - - - - - 1 1B 1 1 XXXXXXB - - 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Read/Write R/W W R/W W Initial Value XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B
(Continued)
20
MB89550A Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H to 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H to 55H 56H
Abbreviation SSD1 SIDR1/ SODR1 SMC2 CNTR1 CNTR2 CNTR3 COMR1 COMR2 PCR1 PCR2 PLBR SMC21 SMC22 SSD2 SIDR2/ SODR2 SRC2 ADC1 ADC2 ADDL ADDH TMCR TCHR TCLR EIC1 EIC2 EIC3 EIC4 DACR DADR1 DADR2 EIE2
Resister Name Serial status and data register (UART) Serial input/serial output data register (UART) Serial mode control register 2 (UART) PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register Serial mode control register 1 (UART/SIO) Serial rate control register 2 (UART/SIO) Serial status and data register (UART/SIO) Serial input/serial output date register (UART/SIO) Baud rate generator reload register (UART/SIO) A/D control register 1 A/D control register 2 A/D data register low A/D data register high Unused area Timer control register (16-bit timer/counter) Timer count register high (16-bit timer/counter) Timer count register low (16-bit timer/counter) External interrupt register 1 External interrupt register 2 External interrupt register 3 External interrupt register 4 D/A control register D/A data register 1 D/A data register 2 Unused area External interrupt 2 control register
Read/Write R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 1 0 0 - 1XB XXXXXXXXB - - 1 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 X 0 0 0 0B X 0 0 0 XXXXB XXXXXXXXB XXXXXXXXB 0 0 0 XX 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 1 XXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B X 0 0 0 0 0 0 1B XXXXXXXXB 0 0 0 0 0 0 XXB XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXX 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B
(Continued)
21
MB89550A Series
(Continued) Address
57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 ADEN
Abbreviation EIF2 RCR1 RCR2 CKR LCR1 LCR2 LCR3 LCD1 LCD2 VRAM SMR SDR PORR0 PURR1 PURR2 PURR4 PURR8 WREN
Resister Name External interrupt 2 flag register 6-bit PPG control register 1 6-bit PPG control register 2 Clock output control register LCDC control register 1 LCDC control register 2 LCDC control register 3 LCD static display register 1 LCD static display register 2 LCD display RAM Serial mode register (8-bit serial I/O) Serial data register (8-bit serial I/O) Port 0 pull-up option setting register Port 1 pull-up option setting register Port 2 pull-up option setting register Port 4 pull-up option setting register Port 8 pull-up option setting register Wild register/address comparator enable register Unused area A/D port input enable register Unused area Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Unused area
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W
Initial Value XXXXXXX 0B 0 0 0 0 0 0 0 0B 0 - 0 0 0 0 0 0B XXXXXX 0 0B 0 0 0 1 0 0 0 0B 0 0 0 0 0 0 0 0B - - - 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB 11111111B 11111111B 11111111B 11111111B 11111111B - - 0 0 0 0 0 0B 11111111B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B
22
MB89550A Series
* Extended I/O Area Address Abbreviation 480H 481H 482H 483H 484H 485H 486H 487H 488H 489H 48AH 48BH 48CH 48DH 48EH 48FH 490H 491H WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 WRARH4 WRARL4 WRDR4 WRARH5 WRARL5 WRDR5 WRARH6 WRARL6 WRDR6
Resister Name H address setting register 1 L address setting register 1 Data setting register 1 H address setting register 2 L address setting register 2 Data setting register 2 H address setting register 3 L address setting register 3 Data setting register 3 H address setting register 4 L address setting register 4 Data setting register 4 H address setting register 5 L address setting register 5 Data setting register 5 H address setting register 6 L address setting register 6 Data setting register 6
Read/Write R/W R/W W R/W R/W W R/W R/W W R/W R/W W R/W R/W W R/W R/W W
Initial Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
O Read/write notation * R/W : Reading and writing enabled *R : Read-only *W : Write only O Initial value notation * 0 : Initial value of bit is "0". * 1 : Initial value of bit is "1". * X : Initial value of bit is undefined. Note : Areas indicated as "unused area" are not to be used.
23
MB89550A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max VSS + 4.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC2 + 0.3 V3 VSS + 6.0 VCC2 V3 VSS + 6.0 15 30 (AVss = Vss = 0 V) Unit V V V V On models without step-up circuits V0-V3 are not to exceed VCC2. Pins other than P50 to P57, P60 to P67, P70 to P77, P46, P47, P30, P31 P50 to P57, P60 to P67, P70 to P77 P46, P47, P30, P31 Pins other than P50 to P57, P60 to P67, P70 to P77, P46, P47, P30, P31 P50 to P57, P60 to P67, P70 to P77 P46, P47, P30, P31 Pins other than P22/UCK, P23/ PPG1 P22/UCK, P23/PPG1 Pins other than P22/UCK, P23/ PPG1 average value (operating current x operating ratio) P22/UCK, P23/PPG1 average value (operating current x operating ratio) VCC1 not to exceed VCC2.* Remarks
Parameter Power supply voltage A/D converter reference input voltage D/A converter reference input voltage LCD power supply voltage
Symbol VCC1 VCC2 AVR DVR V0-V3
VI1 Input voltage VI2 VI3 VO1 Output voltage VO2 VO3 "L" level maximum output current IOL1 IOL2
V V V V V V mA mA
IOLAV1 "L" level average output current IOLAV2 "L" level total maximum output current "L" level total average output current "H" level maximum output current IOL IOLAV IOH1 IOH2
4
mA

15
mA
100 60 -15 -30
mA mA mA mA average value (operating current x operating ratio) Pins other than P22/UCK, P23/ PPG1 P22/UCK, P23/PPG1
(Continued)
24
MB89550A Series
(Continued)
Parameter Symbol Rating Min Max -4 Unit Remarks Pins other than P22/UCK, P23/ PPG1 and open drain output pins average value (operating current x operating ratio) P22/UCK, P23/PPG1 average value (operating current x operating ratio)
IOHAV "H" level average output current IOHAV "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature IOH IOHAV PD TA Tstg
mA
-40 -55
-15 -50 -30 300 +85 +150
mA
mA mA mW C C average value (operating current x operating ratio)
* : Set AVCC to the same potential as VCC. Also ensure that AVR and DVR do not exceed AVCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
25
MB89550A Series
2. Recommended Operating Conditions
Rating Min 2.2*1 2.2* 2.7*2 1.5 VCC1 VCC1
1
(AVss = Vss = 0 V) Max 3.6 5.5 5.5 3.6 AVCC AVCC Unit V V V V V V V Remark Guaranteed normal operating range (MB89557A/558A) Guaranteed normal operating range (MB89P558A) To maintain RAM state in stop mode Guaranteed normal operating range Guaranteed normal operating range Models without step-up circuit, pins V0 to V3. LCD power supply range and maximum value are determined by the characteristics of the LCD display element used.
Item
Symbol VCC1 VCC2
Power supply voltage*
3
VCC1 VCC2 VCC1, VCC2
A/D converter reference voltage input*4 D/A converter reference voltage input*4
AVR DVR
LCD supply voltage
V0-V3
VSS
VCC2
V
Operating temperature
TA
-40
+85
C
*1 : The operating power supply voltage differs depending on the instruction cycle time of the operating frequency. See Figure 1. *2 : The operating power supply voltage differs depending on the instruction cycle time of the operating frequency. See Figure 2. Note also that on the MB89PV550A the input to the VCC1 pin is cut off internally, and on the MB89P558A the VCC1 pin is used as the VPP pin for on-board writing. *3 : AVcc and VCC2 should be set to the same potential. Also, care must be taken to ensure that VCC1 does not exceed VCC2. *4 : Care must be taken to ensure that the relation between AVR and DVR is such that "VCC1 AVR (DVR) AVCC + 0.3 V".
26
MB89550A Series
Figure 1. Operating Voltage vs. Operating Frequency (MB89558A/557A)
6 6
5
5
Operating voltage (VCC1)
4
4
3
MB89557A/MB89558A*
3
2
2
1
1
Operating frequency (MHz) (at instruction cycle = 4 / Fc)
4.0 2.0 0.8 0.4 0.32
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
Instruction cycle
(s) * : Analog precision warranted range : AVCC = 3.5 V to 5.5 V
: TA = -40 C +85 C
Figure 2. Operating Voltage vs. Operating Frequency (MB89P558A)
6 6
5
5 MB89P558A*
Operating voltage (VCC2)
4
4
3
3
2
2
1
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
Operating frequency (MHz) (at instruction cycle = 4 / Fc)
4.0 2.0 0.8 0.4 0.32
Instruction cycle
(s) * : VCC2 = 2.2 V to 5.5 V (VCC2 VCC1) Analog precision warranted range : AVCC = 3.5 V to 5.5 V
: TA = -40 C +85 C : TA = -10 C +55 C : TA = +25 C
27
MB89550A Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
28
MB89550A Series
3. DC Characteristics
Symbol
VIH1
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Pin name Condition Value Min 0.7 VCC2 Typ Max VCC2 + 0.3 V3 VSS + 5.5 VCC2 + 0.3 Unit Remarks
Parameter
P00 to P07, P10 to P17, P20 to P27, P40 to P45, P80 to P87 P50 to P57, P60 to P67, P70 to P77 P46, P47, P30, P31 INT10 to INT17, UI, UCK, INT20 to INT27, SCK, EC1, EC2, EC3, RST, MODA SI, PWC P00 to P07, P10 to P17, P20 to P27, P30, P31, P40 to P47, P80 to P87 P50 to P57, P60 to P67, P70 to P77 INT10 to INT17, UI, UCK, INT20 to INT27, SCK, EC1, EC2, EC3, RST, MODA, SI, PWC P46, P47, P30, P31 P50 to P57, P60 to P67, P70 to P77

V VIH2 not to exceed V3.
VIH2
0.7 VCC2 0.7 VCC2
V V
"H" level input voltage
VIH3
VIHS1
0.8 VCC2
V
Hysteresis input Hysteresis input
VIHS2

0.8 VCC2 VSS - 0.3 VSS - 0.3

VSS + 5.5 0.3 VCC2
V
VIL1
V VIL2 not to exceed V3. Hysteresis input
"L" level input voltage
VIL2
0.3 VCC2
V
VILS

VSS - 0.3 VSS - 0.3 VSS - 0.3

0.2 VCC2 VSS + 5.5 V3
V
Voltage applied to open drain output pins
VD1 VD2
V V VD2 not to exceed V3.
"H" level output voltage
VOH1
P00 to P07, P10 to P17, IOH = P20, P21, P24 to P27, -2.0 mA P40 to P45, P80 to P87 P22, P23 IOH = -4.0 mA
4.0

V
VOH2
4.0
V
"L" level output voltage
VOL1
P00 to P07, P10 to P17, P20, P21, P24 to P27, IOL = P30, P31, P40 to P47, 4.0 mA P50 to P57, P60 to P67, P70 to P77, P80 to P87 P22, P23 IOL = 12 mA P00 to P07, P10 to P17, P20 to P27, P30, P31 0.0V < VI < P40 to P47, P50 to P57, VCC2 P60 to P67, P70 to P77, P80 to P87, MODA
0.4
V
VOL2
0.4
V Without pull-up resistor option
Input leak current (Hi-Z output leak current)
ILI
5
A
(Continued)
29
MB89550A Series
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Parameter Pull-up resistance Symbol Pin name Condition Value Min 25 Typ 50 Max 100 Unit Remarks With pull-up resistor option tinst = 0.32 s MB89557A/ 558A tinst = 0.32 s MB89P558A tinst = 6.4 s MB89557A/ 558A tinst = 6.4 s MB89P558A
P00 to P07, P10 to P17, RPULL P20 to P27, P40 to P45, VI = 0.0 V P80 to P87, RST VCC1 ICC1 VCC2 VCC1 = 3.0 V VCC2 = 5.0 V FCH = 12.5 MHz VCC2 = 5.0 V FCH = 12.5 MHz VCC1 = 3.0 V VCC2 = 5.0 V FCH = 10.0 MHz VCC2 = 3.0 V FCH = 10.0 MHz VCC1 = 3.0 V VCC2 = 3.0 V FCH = 12.5 MHz VCC2 = 5.0 V FCH = 12.5 MHz VCC1 = 3.0 V VCC2 = 3.0 V FCH = 10.0 MHz VCC2 = 3.0 V FCH = 10.0 Hz VCC1 = 3.0 V VCC2 = 5.0 V FCL = 32 kHz TA = + 25 C VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C VCC1 = 3.0 V VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C
k

4.5
6
mA
22
25
mA
VCC1 ICC2 VCC2
1.4
2.1
mA
5.3
9
mA
VCC1 ICCS1 VCC2
2
3
Sleep mode tinst = 0.32 s mA MB89557A/ 558A Sleep mode mA tinst = 0.32 s MB89P558A Sleep mode tinst = 6.4 s mA MB89557A/ 558A mA Sleep mode tinst = 6.4 s MB89P558A Sub-mode MB89557A/ 558A Sub-mode MB89P558A Sub-sleep mode MB89557A/ 558A Sub-sleep mode MB89P558A
6.2
10
Power supply current ICCS2
VCC1
0.35
1
VCC2
0.6
2
VCC1 ICCL VCC2
30
50
A
4
8
mA
VCC1 ICCLS VCC2
10
20
A
20
50
A
(Continued)
30
MB89550A Series
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Condition VCC1 = 3.0 V VCC2 = 3.0 V TA = + 25 C FCL = 32 kHz VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C VCC1 = 3.0 V VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C VCC2 = 3.0 V FCL = 32 kHz TA = + 25 C VCC1 = 3.0 V AVCC = VCC2 = 5.0 V FCH = 12.5 MHz VCC2 = 5.0 V FCH = 12.5 MHz VCC1 = 3.0 V, AVCC = VCC2 = 5.0 V FCH = 12.5 MHz TA = + 25 C VCC2 = 5.0 V FCH = 12.5 MHz TA = + 25 C VCC to V0 at VCC = 5 V Value Min Typ Max Unit Remarks Clock mode Main stop MB89557A/ 558A Clock mode Main stop MB89P558A TA = +25 C Sub- stop MB89557A/ 558A TA = +25 C Sub- stop MB89P558A
VCC1 ICCT VCC2
5
15
A
12
25
A
VCC1 ICCH VCC2 Power supply current IA AVCC
5
10
A
5
10
A
AVCC
2
5
A/D converter running mA MB89557A/ 558A mA A/D converter running MB89P558A TA = +25 C A/D converter stopped MB89557A/ 558A TA = +25 C A/D converter stopped MB89P558A
3
6
AVCC IAH AVCC
10
A
10
A
LCD divider resistance COM0 to COM3 output impedance SEG0 to SEG31 output impedance LCD leak current
RLCD
500
k
RVCOM COM0 to COM3 V1 to V3 = 5 V RVSEG SEG0 to SEG31
5
k
15
k
V0 to V3, ILCDL COM0 to COM3, SEG0 to SEG31
5
A
(Continued)
31
MB89550A Series
(Continued)
Parameter LCD step-up output voltage Reference voltage input impedance Input capacitance V1 input voltage Symbol VOV3 V3 VOV2 V2 RRIN V1 Pin name Condition Value Min 600 Typ 4.5 3.0 1000 Max 1400 Unit V V k Remarks Models with step-up circuits only Models with step-up circuits only
V1 = 1.5 V
CIN
Pins other than VCC,VSS FCH = 1 MHz V1 IIN = 0 A
10
pF Models with step-up circuits only
VI1
1.5
V
32
MB89550A Series
4. AC Characteristics
(1) Reset Timing (DVR = VCC1 = 3 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Symbol tZLZH Confition Rating Min 48 tHCLY Max Unit ns Remarks
Parameter RST "L" pulse width
Note : tHCLY is the main clock oscillator period.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset Rating Min 0.05 1
(AVss = Vss = 0 V, TA = -40 C to +85 C) Symbol tR tOFF Confition Max 50 Unit ms ms For repeated operation Remarks
Parameter Power supply rise time Power supply cutoff time
Note : Be sure that the power supply rise time is less than the selected oscillator stabilization period. Also, when varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually.
tR 1.8 V
tOFF
VCC1, VCC2
0.2 V
0.2 V
0.2 V
On the MB89PV550A and MB89548A oscillation begins and the power-on reset is applied on the rise of the VCC2.On the MB89558A and MB89557A, oscillation begins and the power-on reset is applied on the rise of the VCC1.
33
MB89550A Series
(3) Power Supply Voltage
VCC2 VCC1 0V
Be sure that the power supply is set so that VCC2 VCC1. The MB89PV550A and MB89P558A operate on the VCC2 power supply only. On the MB89558A and MB89557A, VCC1 is the power supply for internal CPU operation, and VCC2 is the I/O power supply.
(4) Clock Timing (AVss = Vss = 0 V, TA = -40 C to +85 C) Parameter Clock frequency Clock cycle time Symbol Pin Name FCH FCL tHCYL tLCYL PWH1 PWL1 PWH2 PWL2 tCR tCF X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Condition Value Min 1 80 20 Typ 32.768 30.5 15.2 Max 12.5 1000 10 Unit MHz kHz ns s ns s ns External clock External clock External clock Remarks
Input clock pulse width
Input clock rise, fall time
34
MB89550A Series
* X0 and X1 clock timing and input conditions
tHCYL PWH1 tCR 0.8 VCC 0.8 VCC tCF PWL1
X0
0.2 VCC 0.2 VCC 0.2 VCC
* Clock configurations When using a crystal oscillator or ceramic oscillator
X0 X1 FCH C1 C2
When using an external clock
X0
X1
Open
FCH
35
MB89550A Series
* X0A and X1A clock timing conditions
tLCYL PWH2 tCR 0.8 VCC 0.8 VCC tCF PWL2
X0A
0.2 VCC 0.2 VCC 0.2 VCC
* Clock configurations When using a crystal oscillator or ceramic oscillator
X0A X1A FCL C1 C2
When using an external clock
X0A
X1A
Open
FCL
(5) Instruction Cycle Parameter Symbol Value
(AVss = Vss = 0 V, TA = -40 C to +85 C) Unit s s Remarks Operating at FCH = 12.5 MHz (4/FCH) tinst = 0.32 s Operating at FCL = 32.768 kHz tinst = 61.036 s
Instruction cycle (minimum instruction execution time)
4/FCH, 8/FCH, 16/FCH, 64/FCH, tinst 2/FCL
Note : Instruction execution time settings differ for 12.5 MHz operation.
36
MB89550A Series
(6) Serial I/O timing
(VCC1 = 3.0 V, AVCC = AVR = DVR = VCC2 = 5 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin Nme SCK, UCK SCK, SO, UCK, UO SI, SCK SCK, SI, UCK, UI SCK, UCK SCK, SO, UCK, UO SI, SCK, UI, UCK SCK, SI, UCK, UI External clock operation Internal clock operation Condition Value Min 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max +200 200 Unit s ns s s s s ns s s Remarks
Parameter Serial clock cycle time SCKSO time UCKUO time Valid SISCK Valid UIUCK SCK valid SI hold time UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCKSO time UCKUO time Valid SISCK Valid UIUCK SCK valid SI hold time UCK valid UI hold time * Internal shift clock mode
* : For a definition of tinst see " (5) Instruction Cycle".
tSCYC
SCK UCK
0.8 V tSLOV
2.4 V 0.8 V
SO UO
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
SI UI
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 0.2 VCC 0.8 VCC
SCK UCK
SO UO
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
SI UI
0.8 VCC 0.2 VCC
37
MB89550A Series
(7) Peripheral Input Timing (VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = -40 C to +85 C) Parameter Peripheral input "H" level pulse width 1 Peripheral input "L" level pulse width 1 Peripheral input "H" level pulse width 1 Peripheral input "L" level pulse width 1 Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 Pin Nme EC1, EC2, EC3 INT10 to INT17 EC1, EC2, EC3 INT10 to INT17 PWC, INT20 to INT27 PWC, INT20 to INT27 Condition Value Min 1 tinst* 1 tinst* 2 tinst* 2 tinst* Max Unit s s s s Remarks
* : For a definition of tinst see " (5) Instruction Cycle".
tIHIL1 tILIH1 0.8 VCC 0.8 VCC
EC1, EC2, EC3 INT10 ~ INT17
0.2 VCC
0.2 VCC
tIHIL2
tILIH2 0.8 VCC 0.8 VCC
INT20 ~ INT27, PWC
0.2 VCC
0.2 VCC
38
MB89550A Series
(8) Electrical Characteristics for the A/D Converter (VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = -40 C to +85 C) Item Resolution Total error Linearity error Differential linearity error Zero transition voltage Full scale transition voltage Variation between channels Conversion time Sampling time Analog input current Analog input voltage Reference voltage Reference voltage supply current * : Includes sampling time. (9) Electrical Characteristics for the D/A Converter (VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = -40 C to +85 C) Item Resolution Differential linearity error Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance IDVR IDVRS DVR D/A running D/A off AVR = AVCC Symbol Pin Nme Condition Rating Min VSS + 3.0 Typ 8 10 120 20 30 Max 0.9 1.5 20 AVCC 300 10 Unit bit LSB LSB s V A A k k *2 *3 MB89P558A MB89558A/ 557A *1 Remarks IAIN VAIN IR IRH AVR A/D operating A/D stop AN0 to AN7 VOT VFST AN0 to AN7 AVR = AVCC Symbol Pin Nme Condition Rating Min AVSS - 3.5 AVSS AVSS + 2.7 Typ 10 + 0.5 60 tinst 16 tinst 400 Max 5.0 2.5 1.9 Unit Remarks bit LSB LSB LSB
AVSS + 4.5 LSB 4 10 AVR AVCC 5 LSB s s A V V A A *
AVR - 6.5 AVR - 1.5 AVR + 1.5 LSB
*1 : With load capacitance 20 pF. *2 : No-load conversion *3 : Stop mode 39
MB89550A Series
(10) A/D Converter Glossary * Resolution The level of analog variation that can be recognized by the A/D converter. * Linearity error (Unit : LSB) The deviation between the actual conversion characteristics and the line linking the zero transition point ("00 0000 0000""00 0000 0001") and the full-scale transition point ("11 1111 1110""11 1111 1111") . * Differential linearity error (Unit : LSB) The variation from the theoretical input voltage required to change the output code by 1 LSB. * Total error (Unit : LSB) The total error is the difference between the actual value and the theoretical value. Theoretical I/O characteristics
3FF 3FE VFST 3FF 3FE
Total error
Actual conversion characteristic
(1 LSB x N + 0.5 LSB)
Digital output
004 003 002 001 0.5 LSB AVSS AVR VOT 1 LSB
Digital output
3FD
1.5 LSB
3FD
004 VNT 003 002 001 AVSS
Actual conversion characteristic Theoretical characteristic
AVR
Analog input VFST - VOT 1022
Analog input VNT - {1 LSB x N + 0.5 LSB} 1 LSB
1 LSB =
(V)
Total error for digital output N =
(Continued)
40
MB89550A Series
(Continued)
Zero transition error
004
Full-scale transition error
Theoretical characteristic
Actual conversion characteristic
003
3FF
Actual conversion characteristics
Digital output
Digital output
3FE
002
Actual conversion characteristics
001
3FD
VFST (actual measured value) Actual conversion characteristics
VOT (actual measured value)
AVSS
3FC
Analog input
Analog input
AVR
Linearity error
3FF 3FE
Differential linearity error
Theoretical characteristic
N+1
Actual conversion characteristics
(1 LSB x N + VOT) VFST (actual measured VNT value)
Digital output
Digital output
3FD
Actual conversion characteristic
N
V (N + 1) T
004 003 002 001
Actual conversion characteristics Theoretical characteristic VOT (actual measured value)
N-1
VNT
N-2 AVSS
Actual conversion characteristic
AVSS
AVR
Analog input Linearity error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Analog input
AVR
Differential linearity = V (N + 1) T - VNT -1 1 LSB errorin digital output N
41
MB89550A Series
(11) Notes for A/D Conversion * Analog input pins and input impedance The A/D converter in the MB89550A series incorporates a sample & hold circuit as shown below. When an A/ D conversion starts, the voltage at the analog input pin is captured by the sample & hold capacitor for a period of 16 instruction cycles. Accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog input voltage may not stabilize within the period of the analog input sampling time. Therefore, it is recommended that the output impedance of the external circuit be sufficiently low (10 k or less) . * Equivalent circuit for MB89558A and MB89557A analog input Sample & hold circuit
C = 30 pF
Analog input pin
R = 3.2 k
Comparator Closed for approximately 16 instruction cycles after start of A/D conversion Analog channel selector
* Equivalent circuit for MB89P558A and MB89PV550A analog input Sample & hold circuit
C = 64 pF
Analog input pin
R = 1.4 k
Comparator Closed for approximately 16 instruction cycles after start of A/D conversion Analog channel selector
* Error The relative error increases as AVR - AVSS becomes smaller.
42
MB89550A Series
s EXAMPLE CHARACTERISTICS
(1) Power Supply Current (External Clock)
ICC - VCC1 10 (TA = + 25 C) 8 10 (TA = + 25 C) 8 ICCS - VCC1
FC = 12.5 MHz, 4 division
6 ICC [mA] ICCS [mA]
6
FC = 12.5 MHz, 4 division
4
4
2
2
FC = 10 MHz, 64 division
0 1 2 3 VCC1 [V] 4 5 1 2
FC = 10 MHz, 64 division
3 VCC1 [V] 4 5
0
(2) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
VIN - VCC2 4 (TA = + 25 C) 3 VIN [V]
2
1
0 2 3 4 VCC2 [V] 5 6 7
(3) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN - VCC2 4 (TA = + 25 C) VIHS 3 VIN [V]
2
VILS
1
0 2 3 4 VCC2 [V] 5 6 7
43
MB89550A Series
(4) Pull-up Resistance
RPULL - VCC2 1000 (TA = + 25 C)
Pull-up [k]
100
10
1 2 3 4 VCC2 [V] 5 6 7
(5) "H" Level Output Voltage
VOH1 - IOH 4.6 (VCC2 = 4.5 V, TA = + 25 C) 4.4 4.2 4.0 VOH1 [V] 3.8 3.6 3.4 3.2 3.0 0 -2 -4 -6 IOH [mA] -8 - 10 3.8 0 -5 - 15 - 10 IOH [mA] - 20 - 25 4.0 VOH2 [V] 4.4 4.6 (VCC2 = 4.5 V, TA = + 25 C) VOH2 - IOH
4.2
(6) "L" Level Output Voltage
VOL1 - IOL 1.0 (VCC2 = 4.5 V, TA = + 25 C) 0.8 VOL2 [V] 0.6 0.4 0.2 0.0 0 2 4 IOL [mA] 6 8 10 0.8 0.6 0.4 0.2 0.0 0 5 10 IOL [mA] 15 20 25 1.0 (VCC2 = 4.5 V, TA = + 25 C) VOL2 - IOL
44
VOL1 [V]
MB89550A Series
(7) A/D Converter Characteristic Example Liniarity error
3.0 2.5 2.0 1.5
(VCC2 = 5.0 V, FC = 12.5 MHz, TA = + 25 C)
Error (LSB)
1.0 0.5 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 - 3.0
0
100
200
300
400
500
600
700
800
900
1000
Conversion characteristics
Differential liniarity error
3.0 2.5 2.0 (VCC2 = 5.0 V, FC = 12.5 MHz, TA = + 25 C)
Error (LSB)
1.5 1.0 0.5 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 - 3.0
0
100
200
300
400
500
600
700
800
900
1000
Conversion characteristics
45
MB89550A Series
s MASK OPTIONS
Part No. No. Specifying procedure MB89557A MB89558A Specify when ordering mask MB89P558A Specify at time of order -201 built-in multiplier resistance Selectable -202 built-in step-up circuit -203 built-in step-up circuit MB89PV550A Specify at time of order -201 built-in multiplier resistance -202 built-in step-up circuit -203 built-in step-up circuit
1
LCD drive power supply * Built-in step-up circuit * Built-in multiplier resistance (for external connection)
2
Port/segment selection*1 P66 (SEG22) , P67 (SEG23) , P70 (SEG24) , P71 (SEG25) , P72 (SEG26) , P73 (SEG27) , P74 (SEG28) , P75 (SEG29) , P76 (SEG30) , P77 (SEG31) Main clock Initial value*2 selection for oscillator stabilization wait period (Fch = 12.5 MHz) * 01 : 214/Fch (approx. 1.31 ms) * 10 : 217/Fch (approx. 10.48 ms) * 11 : 218/Fch (approx. 20.97 ms)
-201 segment selected -201 segment selected (SEG22-SEG31 selected) (SEG22-SEG31 selected) Selectable -202 segment selected -202 segment selected (SEG22-SEG31 selected) (SEG22-SEG31 selected) -203 port selected (P66, P67, P70-P77 selected) -203 port selected (P66, P67, P70-P77 selected)
3
Selectable
218/Fch (approx. 20.97 ms)
218/Fch (approx. 20.97 ms)
*1 : This selection determines whether pins P66, P67, P70-P77 are used as I/O ports or as segment output pins. If they are used as ports, then SEG22-SEG31 (Nch open drain) are not restricted by the condition for input voltage to pins (VIN), namely that "VIN must be lower than the voltage at the V3 pin". *2 : This represents the initial value of the oscillator stabilization period select bit (SYCC : WT1, WT0) of the system clock control register.
46
MB89550A Series
s ORDERING INFORMATION
Part No. MB89558APFV-XXX MB89558APFT-XXX MB89P558A-201PFV versions without step-up MB89P558A-202PFV with step-up 32 Segment MB89P558A-203PFV with step-up 22 Segment MB89P558A-201PFT versions without step-up MB89P558A-202PFT with step-up 32 Segment MB89P558A-203PFT with step-up 22 Segment MB89PV550A-201CF versions without step-up MB89PV550A-202CF with step-up 32Segment MB89PV550A-203CF with step-up 22Segment Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic TQFP (FPT-100P-M18) 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic TQFP (FPT-100P-M18) 100-pin Ceramic MQFP (MQP-100C-P02) Remarks
47
MB89550A Series
s PACKAGE DIMENSIONS
100-pin plasic LQFP (FPT-100P-M05) Note) Pins width and pins thickness include plating thickness.
16.000.20(.630.008)SQ 14.000.10(.551.004)SQ
75 51
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2000 FUJITSU LIMITED F100007S-3c-5
Dimensions in mm (inches)
(Continued)
48
MB89550A Series
100-pin plasic TQFP (FPT-100P-M18)
14.000.20(.551.008)SQ 12.000.10(.472.004)SQ
75 51
Note) Pins width and pins thickness include plating thickness.
0.1450.055 (.006.002)
76
50
0.08(.003)
Details of "A" part 1.100.10 (.043.004) INDEX
100 26
0~8 "A"
0.100.05 (.004.002) (Stand off)
0.25(.010) LEAD No.
1 25
0.600.15 (.024.006) 0.07(.002)
M
0.40(.016)
0.180.05 (.007.002)
C
2000 FUJITSU LIMITED F100029S-c-2-3
Dimensions in mm (inches)
(Continued)
49
MB89550A Series
(Continued) 100-pin Ceramic MQFP (MQP-100C-P02)
PIN No.1 INDEX
15.000.25 SQ (.591.010) 14.820.35 SQ (.583.014)
0.30(.012) TYP 1.020.13 (.040.005)
0.500.15 (.0197.0060) 0.180.05 (.007.002)
10.92(.430) TYP
7.14(.281) TYP
12.00(.472) 17.20(.667) TYP TYP
4.50(.177)SQ TYP 10.92(.430) TYP
PAD No.1 INDEX 1.10 -0.25 .043 -.010
+0.45 +.018
12.00(.472)TYP 17.20(.667)TYP
9.94(.392)MAX
0.150.05 (.006.002)
C
1994 FUJITSU LIMITED M100002SC-2-2
Dimensions in mm (inches)
50
MB89550A Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0205 (c) FUJITSU LIMITED Printed in Japan

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